EE203 Digital Systems, Fall 2018

This course emphasizes high-level aspects of "digital systems design" -- as the word "systems" in the course name implies. In that context, it is critical to understand analog vs digital, sensors, system I/O, waveforms, timing, area, power, and cost issues. As modern digital design problems are large, they can only be addressed with a scalable hence language based approach. In this course, we will write digital designs in Verilog language (similar to C) for the most part and map them to FPGAs. In the lab, we will also implement digital circuits with discrete components . the traditional way, in addition to Verilog on FPGAs.

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Latest NEWS: Final Exam is on Jan 8, Tuesday. Lastnames A-Gokturk in Rm 237, Gonul-Naz 238, Neseli-Z 241. Problem session will be on Monday.

    Dr. H. Fatih Ugurdag email:
    PhD, 1995, Case Western Reserve University

    Midterm 1:
    Midterm 2:
    Class Participation:
    Lecture Attendance:
25% (you get ZERO if you miss 3 labs)
10% (you miss them if you are not attending lectures)
not compulsary (but strongly recommended)

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