Sample Midterm

Q0: Draw the CMOS transistor circuit for !(A.!B+C).

Q1: Given the waveforms of the clock and D inputs of a flop, draw me the waveform for the Q output right underneath the D waveform. (Draw it where Q is marked and make sure your waveform is drawn with respect to the same time axis as clock and D.)

Q2: What is the max clock frequency this circuit can run on? (Do not assume a variation based on PVT and load.)

Q3: Now, let's assume there is a variation based on PVT (but not load). The values in the above figure are for the slow corner. Assume all the delays (except skew) become half in the fast corner. If we barely meet the hold time in the slow corner, how much of a delay buffer do we have to add to this circuit (and where) to make this circuit work even in the fast corner?

Q4: Consider the gate level circuit in the below figure. We know that the delay of a gate equals d_int +d_ext. d_int is a constant number for a given gate. d_ext depends on the load capacitance (C_load) that is being driven. d_ext = C_load.t_ext/C_input. t_ext and C_input are constants for a given gate. The more the C_input, the lower the delay of the gate. However, since C_input becomes part of the C_load of the previous gate, the delay of the previous gate increases. In the below figure, the inverter drives 100 gates where each one has a capacitance 10fF (femto=10 Farads). For the inverter, t_ext is 10ps. For the OR gate before that, t_ext is 20ps and C_input is 400fF. You are free to pick an inverter with any C_input. Adjust the C_input such that the delay from the input of the OR to the fanout of the inverter is the minimum.

Q5: Design me a 5-input NOR so that the delay thru the circuit is the minumum. Your cell library includes only 2-input gates and inverter. The gates you have in the library are AND, NAND, OR, NOR, NOT. The delays are assumed to be constant (since we do not have a big fan-out in the circuit) and are respectively 75, 50, 80, 55, 15. Draw the fastest circuit, show the longest delay thru the circuit, and give the highest frequency this circuit can run on.

Q6: Write the Verilog code for a state machine based digital circuit which produces a single bit output that is 1 for 2 clock cycles, 0 for 3 clock cycles, and repeats this patterm forever. Include a reset input and appropriate code.

Q7: Fix the syntax of this Verilog code.

Q8: Draw the circuit that corresponds to this Verilog code.

Q9a: We intend to compute x=(a+b+c+d).(e+f)+g+h. You have fast adders and multipliers at your disposal. A fast adder takes 5ns and a fast multiplier takes 10ns. When you have two arithmetic units back to back, assume the total delay is the sum of individual delays. What is the minum time you can compute x?

Q9b: Let's assume we have a clock we can adjust. We also have flops, muxes, and basic gates at our disposal. We want to compute x with only 2 adders and a multiplier. What is the fastest time we can compute x? (Ignore all delays except the arithmetic units.) Pick a clock frequency. Show when and where each operation gets executed. (Come up with a schedule.)

Q10: Draw the circuit implementation of Q9.

Q11: Write the Verilog code for it.

Q12: If I pipeline the computation in Q9 so that every cycle a new computation can be started, how many ns will it take to perform the same computation 99 times.

Q13: If the output x of one computation in Q9 enters as b of the next computation. how often can I initiate a new computation?

Q14: If the output x of one computation in Q9 enters as e of the next computation. how often can I initiate a new computation? WHat is the latency and what is the throughput in this case?

Q15: The silicon piece inside an integrated circuit is called
(a) a die
(b) a silicon wafer
(c) a chip
(d) an ASIC
(e) none of the above

Q16: BGA is a type of:
(a) silicon
(b) chip
(c) chip package
(d) chip pins
(e) chip design tool

Q17: Which one is not a simulation tool:
(a) Icarus
(b) Synapticad
(c) DC
(d) Modelsim
(c) VCS

Q18: Placement is before
(a) Routing
(b) Synthesis
(c) Simulation
(d) Static timing
(e) Verification

Q19: One would use an FPGA instead of an ASIC if
(a) volumes are high
(b) volumes are low
(c) speed is key
(d) low power is key
(e) an embedded processor is required

Q20: One of the following is correct:
(a) Tcl/Tk is one of the command languages for Synopsys.
(b) Tcl/Tk is not used for MS Windows GUI development.
(c) Tcl was never used as a web scripting language.
(d) Tcl was developed by a professor who did his PhD in VLSI.
(e) All of the above.

Q21: One of the following is incorrect:
(a) Clock trees in chips are driven by gates with high drive strength.
(b) In CMOS (which most digital chips are) multiple drivers are not allowed except in the case of tristate buffers.
(c) The drive strength of a gate is proportional to its capacitance.
(d) A gate with a high drive strength always reduces the delay.
(e) The output of a tristate buffer when it is not driving its output is specified by z (ie. high-impedance) in Verilog.