Course Info for
EENG 4050 - Intro to VLSI Design
3 credits

Instructor:   Assistant Prof. H. Fatih Ugurdag
Prerequisite: EENG 2003 - Digital Design

Required Textbook:

    Application-Specific Integrated Circuits
    by Michael John Sebastian Smith
    Hardcover with 1026 pages
    Publisher: Addison-Wesley Pub Co; 1st edition (June 10, 1997)
    ISBN: 0201500221
    Weight: 2kg

    Available at Caglayan Bookstore in Beyoglu for a very CHEAP price
    This book sells for 60 to 75 USD in the US. Caglayan Bookstore
    bought 6 copies for you and is selling them for 30 USD + 8%
    KDV. This is cheaper than getting it photocopied. The book is over
    1 000 pages. You may order the book thru Caglayan web page and
    when you order in groups of two you do not even pay for
    cargo. Otherwise, cargo is 3.5YTL. There is a link to order it on
    ugurdag.com. Caglayan will bring in more copies soon.


Course Materials: Handouts (also on reserve in the library)
                  Web material on either of
                     * ugurdag.com/eeng4050
                         (user guest pw konuk)
                     * groups.yahoo.com/group/eeng4050
                         (Please sign up -- you may need a Yahoo id)
                     * course.bahcesehir.edu.tr/icon

* What is this course about?  This course will give you an overview of
  digital chip design. This course will emphasize literacy in chips as
  well as Verilog programming for digital design and verification.

* Email List: eeng4050@yahoogroups.com (sign up -- see above)

* Lecture Hours: Mon 11:30-14:20

* Instructor Office Hours: Mon 14:20-16:30
                           Wed 14:45-16:30

* Grading (see the homepage)

Syllabus: (subject to change)
  Week#1.  Getting to know each other and the course.
       2.  The what/why/how of ICs and ASIC Flow.
           Basics of digital design and Verilog.
       3.  Basics of Verilog.
           More on ASIC Flow.
       4.  Verilog: Non-blocking versus blocking assign.
                    Continuous assign.
                    Function, task.
           FPGAs versus DSP chips. FIR filter example.
           Wave pipelining.
           Resource sharing.
       5.  Gate level timing: CQ delay, Setup, Hold, Clock skew.
                              Gates' intrinsic and extrinsic delays.
           Scheduling. More on resource sharing.
       6.  Simulation lab.
       7.  Logic synthesis.
       8.  Project discussions. Computer arithmetic.
       9.  Review. Midterm.
       10. Project backgrounder: PG Adders, Barrel Shifter, RrArbiter, Median Filter.
       11. Project discussions.
       12. Review of projects. FIFO design.
       13. TBD.
       14. Project submission + presentations.