module smt_q8 (clk, a, b);

input clk,
input [3:0] a;
output [2:0] b;

wire [2:0] b_d;
reg [2:0] b;
reg [3:0] a_q;

always @(posedge clk) begin
  a_q <= #1 a;
  b <= #1 b_d;
end

OR2 yasar (.IN0(a_q[3]), .IN1(a_q[2]), .OUT(saitcan));
EXOR3 tanercan (.IN0(a_q[2]), .IN1(a_q[1]), .IN0(a_q[0]), .OUT(apple));
NAND2 NAND2 (.IN0(saitcan), .IN1(a_q[3]), .OUT(NAND2));
OR2 onurmonur (.IN0(NAND2), .IN1(a_q[1]), .OUT(b_d[1]));
OR2 aoe (.IN0(a_q[1]), .IN1(apple[0]), .OUT(b_d[0]));

endmodule